China-based technology giant Huawei has introduced a new scaling law and chip architecture that will enable the development of chips with a 1.4 nanometer equivalent process node by 2031. The Tau (τ) Scaling Law, announced by the company's science committee chairman and semiconductor business unit head He Tingbo at the 2026 IEEE International Symposium on Circuits and Systems, was presented as a new principle replacing the traditional transistor shrinking method with time scaling. He Tingbo stated that 381 chips have been designed and mass-produced using this law over the past six years. Additionally, an innovative core technology called LogicFolding was introduced. This architecture aims to increase transistor density by reducing resistance and capacitive load in signal propagation. Huawei predicts that its high-performance chips based on this new scaling law will reach transistor densities equivalent to 1.4 nm by 2031. The Kirin chips, planned to be launched this year, will be the first products to adopt the LogicFolding architecture. He expressed expectations for a significant leap by the end of 2026. The company emphasized that it has prepared its technologies, including domestic electronic design automation tools and design methodologies, over six years. Huawei will continue to increase transistor density and raise operating frequencies by reflecting R&D efforts into products between 2026 and 2035. Furthermore, it stated confidence in providing high-quality, low-latency large-scale solutions for artificial intelligence systems. These developments are considered part of Huawei's efforts to establish an independent chip innovation system despite U.S. export restrictions. The company aims to replace foreign technology giants like Nvidia with Ascend AI chips and Kunpeng processors. It plans to launch the Ascend 950, 960, and 970 series AI chips during the 2026-2028 period.